Anders Nielsen on Single-stepping An NMOS 6502 Using RDY and SYNC

I'm having to decipher his video demonstration to figure what this means in terms of the timing diagram, ...

 

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Here's the Apple I version of the circuit Steve Wozniak designed: 

Here's the modern version for CMOS 74 series with the extra pull-up resistors. See Anders' Github page for this project: https://github.com/AndersBNielsen/6502-Single-Cycle-Board.

These flip-flops latch the Data inputs on the Clocks which are positive edge triggered. From the pinouts on the TI Datasheet for the SNx4HC74, we can infer that R and S in these diagrams are what the  data sheets refer to as CLR and PR: see 7474 Dual D Flip-Flop Datasheet.

In addition (5:50), there seems is some confusion over which clock to use. He says "most modern circuits call the inverted input clock Φ1, but actually an inverted Φ0 arrives sooner than a Φ1 coming out the NMOS 6502 would, which means that the timing doesn't work for inspecting instructions since it will actually halt on the clock after the SYNC pulse. Luckily we can still get it to halt at the next instruction if we just use the input clock Φ0 instead". See the Rockwell 6502 Datasheet:


The numeric columns below are min and max values for 1 MHz and 2MHz clocks respectively:

See Some Ideas for a Hardware Project, ...

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