RISC-V Peripheral Idea - A High-Speed LVDS Link for a Modern Transputer

Thinking about the TinyTapeout RISC-V Peripherals experiment: That Pico ICE FPGA Trainer Board will be able to prototype a high-speed serial bus interconnect which could also be the basis for a RISC-V CPU peripheral that would be the moral equivalent of a Transputer serial-link. Each node could be a RISC-V with four links to its neighbours. LVDS drivers like the Analog Devices ADN4665 and ADN4666, connected via low-cost SATA cables. The hardware could handle the 8b/10b encoding and interface to DMA channels, which would be another peripheral that would probably be quite a severe test of the project infrastructure, but for the prototype the FPGA could probably be interfaced with the RP2040's DMA somehow, even if it was just via GPIO pins. There is even a Lattice Reference design for an 8b/10b encoder that you could download and drop-in.

 

45:31 "Is it still relevant?" 

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Then YouTube turned up this 2018 talk by Iann Barron


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Menadue on the Pico transputer:

He was going for signal-level compatibility with the original Transputer links:




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