TinyTapeout RISC-V Peripherals

July 28, 2025

... a collaborative competition to crowdsource the coolest, weirdest, and most useful peripherals for a RISC-V microcontroller. See RISC-V Peripheral Idea - A High-Speed LVDS Link for a Modern Transputer.

The idea is that they fabricate a RISC-V CPU and then each person who enters the competition specifies one or two tiles (1,000 or 2,000 standard digital cells) which implement some particular peripheral. They then connect these peripherals to the CPU via a sort of MUX/Crossbar switch so you can choose which peripherals are connected to which CPU and IO pins when you power-up the silicon.

25:10 In the test harness, I think the peripherals are all driven via an SPI connect from the CPU. So no memory-mapped IO or anything like that, but you will be able to use your peripheral on the RP2040 (on the development board?) via the SPI interface. But in the tapeout the peripheral will have 16 bytes of registers to interface with the CPU.

32:54 There are two possible types of interface: a byte interface which gives you sixteen 8-bit registers and a 32-bit wide interface with 64 bytes of address space and a CPU interrupt line.

Now if they could pretend they were a real hardware manufacturer then they could formally specify that whole mess and allow people to automatically generate drivers (and documentation) for both the RP2040 and RISC-V interfaces. That same formalisation of the interface should be enough to generate the appropriate Verilog HDL for the interface definitions. See Curious Marc - HP LED Display Programmer.

59:32 Mike Bell mentioned the Pico ICE FPGA Trainer, a £27 USB with an RP2040 and a Lattice ICE-40 FPGA. Peter mentioned the https://1bitsquared.de/products/icebreaker.

Links here on Google docs.

See Peter Kinget on the MOSbius, A Field Programmable Transistor Array for Chip Designers.

Submitting an entry. Each peripheral is submitted as a Git pull request on the base Verilog CPU design.